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Masahiro FUKUI, Professor |
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Ritsumeikan University |
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Masahiro FUKUI, Professor |
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Ritsumeikan University |
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| Transaction/Journal Papers | ||
| 18. | M. Ohtsuki, M. Kawai, and M. Fukui, "An efficient algorithm for RTL power macro-modeling and library building," IEICE Transactions on Electronics, vol.E92-C, no.4, pp.- . (Apr. 2009) | |
| 17. | Y. Kawakami, M. Terao, M. Fukui, and S. Tsukiyama, "A power grid optimization algorithm by observing timing error risk by IR drop," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.12, pp.3423-3430. (Dec. 2008) | |
| 16. | Y. Kawakami, K. Kusano, H. Ishijima, M. Terao, and M. Fukui, "An efficient power grid optimization algorithm to secure dependable operation of circuits in manufacture-uncertainty age ," IPSJ Journal, Vol.49 No.6, pp.2144-2154. (Jun. 2008) (in Japanese) | |
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15. |
M. Fukui, S. Iwakoshi, and T. Koyagi, "A power modeling and optimization scheme for future ultra small size electric systems," IEICE Transactions on Electronics, Vol.E90-C, No.10, pp.1900-1908. (Oct. 2007) | |
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14. |
M. Takahashi, H. Miyajima, M. Fukui, "An efficient power and performance evaluation method with the reconfigurable bus architecture model," IPSJ Transactions, 44-5, May 2003. | |
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13. |
M. Tanaka, M. Fukui, ” Circuit optimization for leaf cells,” IPSJ Transaction, 43-5, pp.1323-81329 (May 2002). | |
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12. |
S. Tsukiyama, M. Tanaka, and M. Fukui, "An algorithm for statistical static timing analysis considering correlations between delays," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No.11, pp.2746-2754, Nov. 2001. | |
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11. |
S. Saika, M. Fukui, M. Toyonaga, and T. Akino, "WSSA: A high performance simulated annealing and its application to transistor placement," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E83-A, No.12, pp.2584-2591, Dec. 2000. | |
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10. |
N. Shinomiya, K, Hamawaki, M. Fukui, “An wiring method for leaf cell design,” IPSJ Transactions, 41-4, pp.889-898, Apr. 2000. | |
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9. |
M. Tanaka, M. Fukui, ” A transistor sizing method with precise estimation model of cell area and transistor capacitance,” IPSJ Transactions, 40-4, pp.1644-1650, April 1999. | |
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8. |
M. Fukui, N. Shinomiya, S. Saika, T. Akino, and S. Kuninobu, "Layout abstraction and technology retargeting for leaf cells," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No.12, pp. 2492-2500, Dec. 1998. | |
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7. |
M. Fukui, M. Tanaka, and M. Imai, "Design optimization by using flexible pipeline modules," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No.12, pp. 2521-2528, Dec. 1998. | |
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6. |
T. Shiohara and M. Fukui, "A pin assignment and global routing algorithm for floorplanning," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No.8, pp. 1725-1732, Aug. 1998. | |
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5. |
S. Saika, M. Fukui, N. Shinomiya, and T. Akino, "A two-dimensional placement algorithm for cell synthesis and its application to standard cells," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No.10, pp. 1883-1891, Oct. 1997. |
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4. |
M. Fukui, A. Yamamoto, R. Yamaguchi, and S. Hayama, "SMILE- Hierarchical layout system for building block LSI," International Journal of Computer Aided VLSI Design, Vol. 1, No. 3, pp. 281-302, Mar. 1989. |
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3. |
M. Fukui, A. Yamamoto, R. Yamaguchi, S. Hayama, and Y. Mano, "A block interconnection algorithm for hierarchical layout system," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol.CAD-6, No.3, pp. 383-391, May 1987. |
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2. |
M. Fukui, S. Tsukiyama, and I. Shirakawa, "A pin assigment algorithm for gate array LSIs", IEICE Transactions on Electronics, Vol. J66-C, No. 12, pp. 1172-1179, Dec. 1983. |
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| 1. |
S. Tsukiyama, I. Harada, M. Fukui, and I. Shirakawa, "A new global router for gate array LSI," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol.CAD-2, No. 4, pp. 313-321, Oct. 1983. |
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| International Conference Papers | ||
| 39. | T. Hashizume, H. Sugano, S. Nishizawa, M. Yoshikawa, and M. Fukui, "An efficient hardware accelerator for power grid circuit simulation", in Proc. IEEE International Symposium on Circuits and Systems, pp.- (May. 2009) | |
| 38. | M. Ohtsuki, M. Kawai, H. Kawauchi, and M. Fukui, "An efficient RTL power macro modeling and power estimation scheme," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2009, pp. - . (Mar. 2009) | |
| 37. | T. Hashizume, S. Nishizawa, H. Sugano, M. Yoshikawa, and M. Fukui, "An efficient hardware circuit simulator for power grid optimization system," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2009, pp. - . (Mar. 2009) | |
| 36. | H. Miki, Y. Kawakami, M. Yoshikawa, and M. Fukui, "Reliability aware power grid optimization with consideration of thermal effects," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2009, pp. - . (Mar. 2009) | |
| 35. | Y. Kawakami, M. Fukui, and S. Tsukiyama, "(Invited) Power grid optimization with consideration of timing violation by IR drop ," in Proc. International SoC Design Conference, ISOCC2008, pp.109 - 112. (Nov. 2008) | |
| 34. | Y. Kawakami, M. Fukui, and S. Tsukiyama, "A power grid optimization algorithm with observation of timing error risk by IR Drop," in Proc. IASTED Circuits and Systems, CS2008, pp.37-42. (Aug. 2008) | |
| 33. | T. Koyagi, M. Fukui, and R. Saleh, "Delay Macromodeling and Estimation for RTL", in Proc. IEEE International Symposium on Circuits and Systems, pp.2430-2433 (May 2008) | |
| 32. | Y. Watanabe and M. Fukui, "An accurate and efficient lane recognition algorithm for automobile safety system," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2007, pp. 63 - 68. (Oct. 2007). | |
| 31. | M. Terao, K. Kusano, Y. Kawakami, M. Fukui, and S. Tsukiyama, "A power grid optimization algorithm by direct observation of timing error risk reduction," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2007, pp.310 - 315. (Oct. 2007). | |
| 30. | T. Hashizume, H. Ishijima, and M. Fukui, "An evaluation of circuit simulation algorithms for hardware implementation," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2007, pp.322 - 327. (Oct. 2007). | |
| 29. | T. Hayashi, H. Ishijima, Y. Kawakami, and M. Fukui, "A high-level power grid optimization algorithm by direct observation of manufacturing cost reduction," in Proc. Synthesis and System Integration of Mixed Technologies, SASIMI2007, pp.316 - 321. (Oct. 2007). | |
| 28. | M. Fukui, S. Iwakoshi, and T. Koyagi, "An algorithm for battery modeling and life time maximization of small size electric systems," in Proc. 18th European Conference on Circuit Theory and Design, ECCTD2007, pp.759-762. (Aug. 2007). | |
| 27. | T. Koyagi, M. Fukui, and R. Saleh, "A Flexible Power and Delay Modeling and Optimization for Small Size Systems Operated by Battery", in Proc. International Technical Conference on Circuits/ Systems, Computers and Communications, ITC-CSCC2007, pp.449-450. (Jul. 2007) | |
| 26. | T. Taoka, M. Manabe, and M. Fukui, "An efficient curvature lane recognition algorithm by piecewise linear approach", in Proc. IEEE 65th Vehicular Technology Conference, VTC2007-Spring, pp.2530-2534, (Apr. 2007） |
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| 25. | H. Ishijima, K. Kusano, T. Harada, Y. Kawakami, and M. Fukui, "An algorithm for power grid optimization based on dynamic current consumption," in Proc. IASTED International Conference on Circuits, Signals and Systems (Nov. 2006) |
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24. |
H. Hirai, T. Koyagi, and M. Fukui, "A design optimization scheme for battery operated small size systems," in Proc. IASTED International Conference on Circuits, Signals and Systems (Nov. 2006) |
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23. |
H. Ishijima, T. Harada, K. Kusano, M. Fukui, M. Yoshikawa, and H. Terai, "A Power Grid Optimization Algorithm with Consideration of Dynamic Circuit Operations," in Proc. Synthesis and System Integration of Mixed Technologies (Apr. 2006) |
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22. |
M. Yoshikawa, M. Fukui, H. Terai, ”Immune Algorithm Processor”, Proc. 21st International Conference on Computers and Their Applications, pp.13-18, (Mar. 2006) | |
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21. |
M. Yoshikawa, M. Fukui, H. Terai,” Performance- Driven Floorplanning Technique based on Collaboration of Software and Hardware”, Proc. IEEE Third International Workshop on Intelligent Data Acquisition and Advanced Computing Systems, pp.222-226, 2005. | |
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20. |
M. Takahashi, H. Miyazaki, and M. Fukui, "An efficient power and performance evaluation method with the reconfigurable bus architecture model," in Proc. Synthesis and System Integration of Mixed Technologies, Apr. 2003. | |
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19. |
M. Uehata, M. Tanaka, M. Fukui, and S. Tsukiyama, " False paths Elimination in statistical static timing analysis," in Proc. on The 2002 International Conference on Circuits/Systems Computers and Communications, pp. 357-361, Jul. 2002. | |
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18. |
S. Tsukiyama, M. Tanaka, and M. Fukui, "Techniques to remove false paths in statistical static timing analysis," in Proc. on International Conference on ASIC, pp. 353-358, Sep. 2001. | |
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17. |
S. Tsukiyama, M. Tanaka, and M. Fukui, "A statistical static timing analysis considering correlations between delays," in Proc. on Asia and South Pacific Design Automation Conference, pp. 353-358, Feb. 2001. | |
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16. |
S. Tsukiyama, M. Tanaka, and M. Fukui, "A new statistical static timing analyzer considering correlation between delays," in Proc. on 2002 ACM/IEEE Tau Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Sep. 2000. | |
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15. |
S. Saika, M. Fukui, M. Toyonaga, and T. Akino, "Another high performance simulated annealing and its application to transistor placement," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 107-114, Apr. 2000. | |
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14. |
M. Tanaka, M. Fukui, and S. Kuninobu, "A precise estimation model of cell area and transistor capacitance for transistor size optimization," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 241-247, Oct.1998. |
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13. |
M. Fukui, M. Tanaka, and M. Imai," Design optimization by using flexible pipelined modules," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 176-183, Dec.1997. |
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12. |
S. Saika, M. Fukui, N. Shinomiya, and T. Akino, "A two-dimensional placement for cell synthesis," in Proc. on Asia and South Pacific Design Automation Conference, pp. 557-562, Jan. 1997. |
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11. |
T. Akino, M. Fukui, T. Sawai, and N. Shinomiya, "Relations between logic synthesis and physical synthesis in deep sub-microns," in Proc. International Workshop on IP Based Synthesis and System Design, pp. 33-39, Dec.1995. |
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10. |
M. Fukui, N. Shinomiya, and T. Akino, "A new layout synthesis for leaf cell design," in Proc. Asia and South Pacific Design Automation Conference, pp. 259-264, Aug. 1995. |
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9. |
N. Shinomiya, M. Fukui, and T. Akino, "A new sea-of-cells style layout synthesis," in Proc. Synthesis and System Integration of Mixed Technologies, pp. 17-23, Jul. 1995. |
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8. |
M. Fukui, and A. R. Newton, "Optimum module generation for semi-custom," in Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 184-189, Dec. 1992. |
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7. |
M. Fukui and A. R. Newton, "Multi-output module generation for semi-custom design," in Proc. Synthesis and Simulation Meeting and International Interchange, pp. 181-190, Jun. 1991. |
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6. |
M. Fukui, Y. Tanaka, and T. Akino, " An algorithm for power and ground routing in building block VLSI," in Proc. Synthesis and Simulation Meeting and International Interchange, pp. 294-299, Jan. 1990. |
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5. |
M. Fukui, A. Yamamoto, R. Yamaguchi, S. Hayama, and Y. Mano, " A new routing algorithm for building block layout system," in Proc. European Conference on Circuit Theory and Design, pp. 447-452, Sep. 1987. |
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4. |
M. Fukui, S. Hayama, and Y. Mano "A new block interconnection algorithm for VLSI layout system," in Proc. International Symposium on Circuits and Systems, pp. 1039-1042, Jun. 1985. |
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3. |
S. Tsukiyama, M. Fukui, and I. Shirakawa, "A heuristic algorithm for a pin assignment problem of gate array LSI's," in Proc. International Symposium on Circuits and Systems, pp. 465-469, May 1984. |
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2. |
S. Tsukiyama, I. Harada, M. Fukui, and I. Shirakawa, "A placement and routing algorithms for gate array LSI," in Proc. International Conference on Computer Design: VLSI in Computers, pp.596-599, Oct. 1983. |
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| 1. |
S. Tsukiyama, I. Harada, M. Fukui, I. Shirakawa, and H. Ozaki, "An algorithm of global routing for master slice LSI," in Proc. International Symposium on Circuits and Systems, pp. 1009-1012, May 1982. |
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| US Patents | ||
| 27. | S. Tsukiyama, M. Tanaka, and M. Fukui, "Delay distribution calculation method, circuit evaluation method and false path extraction method", US7131082 (Oct.2006) | |
| 26. | S. Dosho, ..., and M. Fukui, "Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit", US7030688 (April 2006) | |
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25. |
M. Tanaka, S. Tsukiyama, and M. Fukui, "Method of physical design for integrated circuit", US 6,769,098 (Jul. 2004) |
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24. |
M. Fukui and N. Hayashi, "Wiring method", US 6,727,120 (Apr. 2004) |
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23. |
S. Tsukiyama, M. Tanaka, and M. Fukui, "Delay distribution calculation method", US 6,684,375 (Jan. 2004) |
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22. |
K. Hamawaki and M. Fukui, "Routing path finding method", US 6,609,237 (Aug. 2003) |
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21. |
M. Tanaka, M. Fukui, "Method for design of partial circuit", US 6,553,544 (Apr. 2003) |
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20. |
M. Fukui, "Layout structure for integrated circuit", US 6,516,458 (Feb. 2003) |
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19. |
M. Tanaka and M. Fukui, “Method and apparatus for transistor sizing,” US 6,415,417 (Jul. 2002). |
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18. |
M. Tanaka and M. Fukui, “Layout designing apparatus for IC and transistor size determining apparatus,” US 6,393,601 (May 2002). |
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17. |
M. Fukui, “Method and apparatus for designing an LSI layout and cell library,” US 6,336,207 (Jan. 2002). |
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16. |
N. Shinomiya and M. Fukui, “Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring,” US 6,330,707 (Nov.2001). |
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15. |
M. Tanaka and M. Fukui, “Pipeline circuit optimization method,” US 6,292,926 (Sep. 2001). |
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14. |
M. Fukui and M. Tanaka, “Circuit optimization method,” US 6,253,351 (Jun. 2001). |
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13. |
M. Fukui, “Module generation method,” US 6,209,119 (Mar. 2001). |
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12. |
M. Tanaka and M. Fukui, “Semiconductor integrated circuit layout method,” US 6,202,195 (March 2001). |
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11. |
M. Fukui, “Compaction method, compaction apparatus, routing method and routing apparatus,” US 5,943,486 (August 1999). |
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10. |
N. Shinomiya and M. Fukui, “Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height,” US 5,852,562 (December 1998). |
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9. |
M. Fukui, “Cell
generation method and cell generation system,”
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8. |
M. Fukui, “Semiconductor
apparatus and production method,”
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7. |
M. Fukui, “Method and
apparatus for estimating power dissipation and method and apparatus of
determining layout/routing,”
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6. |
M. Fukui, “Layout method
for a semiconductor integrated circuit device,”
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5. |
M. Fukui, “Method and
apparatus for optimizing block shape in hierarchical IC design,”
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4. |
T. Shiohara and M. Fukui,
“System for assigning positions of block terminals in a VLSI,”
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3. |
M. Fukui, “L-shaped
channel wiring method,”
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2. |
M. Fukui, “Layout pattern
generation and geometric processing system for LSI circuits,”
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| 1. |
M. Fukui, “Building block
LSI,”
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Japanese Patents |
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33. |
PAT.3907342, PAT.3543042, PAT.3519584, PAT.3434802, PAT.3453535, PAT.3315391, PAT.3288190, PAT.3217299, PAT.3197245, PAT.3193325, PAT.3177218, PAT.3175532, PAT.3148809, PAT.3135058, PAT.3129883, PAT.3078739, PAT.3073738, PAT.3022198, PAT.3014646, PAT.3013332, PAT.2972705, PAT.2948584, PAT.2938068, PAT.2872990, PAT.2856920, PAT.2752597, PAT.2656840, PAT.2595705, PAT.2506909, PAT.2506907, H06-44594, H07-118506 |
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