// (C) Tomonori Izumi <izumi@ieee.org>, Aug. 2012. All rights reserved.

//  valid/wait ÛÛ p

// Å  producer & consumer

`timescale 1ns / 1ns

// ----------------------------------------------------------------

module producer(xrst,clk,odata,ovalid,owait,p);
   input xrst, clk;
   output [15:0] odata;
   output 	 ovalid;
   input 	 owait;
   input [31:0]  p;  // u

   reg [15:0] 	 odata_reg;
   assign 	 odata=odata_reg;
   reg 		 ovalid_reg;
   assign 	 ovalid=ovalid_reg;

   wire 	 txexec; 
   assign 	 txexec=ovalid && !owait; // 
   
   reg [15:0] 	 datacount_reg;
   reg [31:0] 	 waitcount_reg;
   
   always @(posedge clk or negedge xrst)
     if (!xrst) begin
	odata_reg<=16'hffff;
	ovalid_reg<=0;
	datacount_reg<=0;
	waitcount_reg<=0;
     end else begin
	if (ovalid_reg) begin // Û
	   if (!owait) begin // 
	      datacount_reg<=datacount_reg+1;
	      if (p==0) begin // 
		 odata_reg<=datacount_reg+1;
		 ovalid_reg<=1;
	      end else begin // fÛ
		 odata_reg<=16'hffff;
		 ovalid_reg<=0;
		 waitcount_reg<=p-1;
	      end
	   end
	end else if (waitcount_reg==0) begin // Û¨
	   odata_reg<=datacount_reg;
	   ovalid_reg<=1;
	end else begin // Û
	   waitcount_reg<=waitcount_reg-1;
	end
     end
   
endmodule // producer

// ----------------------------------------------------------------
module consumer(xrst,clk,idata,ivalid,iwait,p);
   input xrst, clk;
   output [15:0] idata;
   input 	 ivalid;
   output 	 iwait;
   input [31:0]  p;  //  

   reg 		 iwait_reg;
   assign 	 iwait=iwait_reg;

   wire 	 rxexec; 
   assign 	 rxexec=ivalid && !iwait; //   

   reg [15:0] 	 idata_reg;
   reg [15:0] 	 datacount_reg;
   reg [31:0] 	 waitcount_reg;
   
   always @(posedge clk or negedge xrst)
     if (!xrst) begin
	iwait_reg<=0;
	idata_reg<=16'hffff;
	datacount_reg<=0;
	waitcount_reg<=0;
     end else begin
	if (!iwait_reg) begin //   
	   if (ivalid) begin //   
	      if (idata!=datacount_reg)
		$display("receive error! rcv %4x exp %4x",
			 idata,datacount_reg);
	      idata_reg<=idata;
	      datacount_reg<=datacount_reg+1;
	      if (p==0) begin //   
		 iwait_reg<=0;
	      end else begin //   
		 iwait_reg<=1;
		 waitcount_reg<=p-1;
	      end
	   end
	end else if (waitcount_reg==0) begin //   
	   iwait_reg<=0;
	end else begin //   
	   waitcount_reg<=waitcount_reg-1;
	end
     end
   
endmodule // consumer

// ----------------------------------------------------------------


module top;
   reg xrst;
   reg clk;
   reg [31:0] ratep, ratec;
   wire [15:0] d1,d2;
   wire        v1,w1,v2,w2;
   reg 	       tmp;
   
   producer prod(xrst,clk,d1,v1,w1,ratep);
   ifsmpl proc(xrst,clk,d1,v1,w1,d2,v2,w2);
   consumer cons(xrst,clk,d2,v2,w2,ratec);
   
   always #5 clk = ~clk;

   always @(negedge clk) begin
      $display("%5d | %b %4x %b | %b %4x %b |",$time,v1,d1,w1,v2,d2,w2);
      //$display("%5d | %b %4x %b | %x | %b %4x %b |",$time,v1,d1,w1,proc.state,v2,d2,w2);
      //$display("%5d | %b %4x %b | %b %4x %b | %b %4x %b | %b %4x %b |",$time,v1,d1,w1,proc.valid1,proc.data1_reg,proc.wait1,proc.valid2,proc.data2_reg,proc.wait2,v2,d2,w2);
   end
   
   initial begin
      $dumpfile("tb_ifsmplvw.vcd");
      $dumpvars;
      clk <= 1'b1;
      xrst=1'b1;
      ratep<=0;
      ratec<=0;
      tmp<=1'b1;
      #2 tmp=~tmp;
      xrst=1'b0;
      #30 tmp=~tmp;
      xrst=1'b1;
      // Á
      #1000 tmp=~tmp;
      // Á
      ratep<=5;
      ratec<=9;
      #1000 tmp=~tmp;
      // Á
      ratep<=9;
      ratec<=5;
      #1000 tmp=~tmp;
      $finish;
   end

endmodule