Synthesis Report for 'hls_regtest2'

General Information

Performance Estimates

• Timing (ns)
  
  
  • Summary
    
    

    Clock	Target	Estimated	Uncertainty
    ap_clk	10.00	3.96	1.25

• Latency (clock cycles)
  
  
  • Summary
    
    

    Latency		Interval		Type
    min	max	min	max
    0	0	1	1	none

  • Detail
    
    
    • Instance
      
      

      N/A

    • Loop
      
      

      N/A

Utilization Estimates

• Summary
  
  

  Name	BRAM_18K	DSP48E	FF	LUT
  Expression	-	-	0	40
  FIFO	-	-	-	-
  Instance	-	-	-	-
  Memory	-	-	-	-
  Multiplexer	-	-	-	32
  Register	-	-	34	-
  Total	0	0	34	72
  Available	270	240	126800	63400
  Utilization (%)	0	0	~0	~0

• Detail
  
  
  • Instance
    
    

    N/A

  • Memory
    
    

    N/A

  • FIFO
    
    

    N/A

  • Expression
    
    

    Variable Name	Operation	DSP48E	FF	LUT	Bitwidth P0	Bitwidth P1
    tmp_2_fu_76_p2	+	0	0	32	32	1
    ap_sig_bdd_41	and	0	0	1	1	1
    tmp_1_fu_65_p2	icmp	0	0	1	2	1
    tmp_3_fu_89_p2	icmp	0	0	3	8	4
    tmp_4_fu_95_p2	icmp	0	0	3	8	5
    Total	5	0	0	40	51	12

  • Multiplexer
    
    

    Name	LUT	Input Size	Bits	Total Bits
    counter_loc_in_phi_fu_51_p4	32	3	32	96
    Total	32	3	32	96

  • Register
    
    

    Name	FF	LUT	Bits	Const Bits
    ap_CS_fsm	1	0	1	0
    counter	32	0	32	0
    run	1	0	8	7
    Total	34	0	41	7

Interface

• Summary
  
  

  RTL Ports	Dir	Bits	Protocol	Source Object	C Type
  ap_clk	in	1	ap_ctrl_none	hls_regtest2	return value
  ap_rst_n	in	1	ap_ctrl_none	hls_regtest2	return value
  ap_return	out	8	ap_ctrl_none	hls_regtest2	return value
  btn	in	8	ap_none	btn	scalar