Synthesis Report for 'hls_strmtest'

General Information

Performance Estimates

• Timing (ns)
  
  
  • Summary
    
    

    Clock	Target	Estimated	Uncertainty
    ap_clk	10.00	7.85	1.25

• Latency (clock cycles)
  
  
  • Summary
    
    

    Latency		Interval		Type
    min	max	min	max
    ?	?	?	?	none

  • Detail
    
    
    • Instance
      
      

      N/A

    • Loop
      
      

      Loop Name	Latency		Iteration Latency	Initiation Interval		Trip Count	Pipelined
      	min	max		achieved	target
      - Loop 1	?	?	2 ~ 12	-	-	?	no

Utilization Estimates

• Summary
  
  

  Name	BRAM_18K	DSP48E	FF	LUT
  Expression	-	-	0	50
  FIFO	-	-	-	-
  Instance	-	-	64	76
  Memory	-	-	-	-
  Multiplexer	-	-	-	35
  Register	-	-	52	-
  Total	0	0	116	161
  Available	270	240	126800	63400
  Utilization (%)	0	0	~0	~0

• Detail
  
  
  • Instance
    
    

    Instance	Module	BRAM_18K	DSP48E	FF	LUT
    hls_strmtest_urem_8s_6ns_8_12_seq_U0	hls_strmtest_urem_8s_6ns_8_12_seq	0	0	64	76
    Total	1	0	0	64	76

  • Memory
    
    

    N/A

  • FIFO
    
    

    N/A

  • Expression
    
    

    Variable Name	Operation	DSP48E	FF	LUT	Bitwidth P0	Bitwidth P1
    c2_fu_168_p2	+	0	0	6	6	6
    grp_fu_158_p0	+	0	0	8	8	8
    n_1_fu_115_p2	+	0	0	8	8	1
    tmp1_fu_101_p2	+	0	0	8	8	8
    p_run_fu_127_p3	Select	0	0	8	1	2
    ap_sig_bdd_163	and	0	0	1	1	1
    ap_sig_bdd_42	and	0	0	1	1	1
    or_cond_fu_147_p2	and	0	0	1	1	1
    tmp_3_fu_121_p2	icmp	0	0	3	8	7
    tmp_4_fu_135_p2	icmp	0	0	3	8	7
    tmp_5_fu_141_p2	icmp	0	0	3	8	7
    Total	11	0	0	50	58	49

  • Multiplexer
    
    

    Name	LUT	Input Size	Bits	Total Bits
    ap_NS_fsm	2	4	2	8
    ap_sig_ioackin_ost_V_TREADY	1	2	1	2
    n_reg_69	8	2	8	16
    run_reg_80	8	2	8	16
    tmp_6_phi_fu_94_p4	8	2	8	16
    tmp_6_reg_91	8	2	8	16
    Total	35	14	35	74

  • Register
    
    

    Name	FF	LUT	Bits	Const Bits
    ap_CS_fsm	2	0	2	0
    ap_reg_ioackin_ost_V_TREADY	1	0	1	0
    n_1_reg_191	8	0	8	0
    n_reg_69	8	0	8	0
    or_cond_reg_206	1	0	1	0
    p_run_reg_201	8	0	8	0
    run_reg_80	8	0	8	0
    tmp1_reg_183	8	0	8	0
    tmp_6_reg_91	8	0	8	0
    Total	52	0	52	0

Interface

• Summary
  
  

  RTL Ports	Dir	Bits	Protocol	Source Object	C Type
  ap_clk	in	1	ap_ctrl_hs	hls_strmtest	return value
  ap_rst_n	in	1	ap_ctrl_hs	hls_strmtest	return value
  ap_start	in	1	ap_ctrl_hs	hls_strmtest	return value
  ap_done	out	1	ap_ctrl_hs	hls_strmtest	return value
  ap_idle	out	1	ap_ctrl_hs	hls_strmtest	return value
  ap_ready	out	1	ap_ctrl_hs	hls_strmtest	return value
  ap_return	out	8	ap_ctrl_hs	hls_strmtest	return value
  idata	in	8	ap_none	idata	scalar
  ist_V_TDATA	in	8	axis	ist_V	pointer
  ist_V_TVALID	in	1	axis	ist_V	pointer
  ist_V_TREADY	out	1	axis	ist_V	pointer
  ost_V_TDATA	out	8	axis	ost_V	pointer
  ost_V_TVALID	out	1	axis	ost_V	pointer
  ost_V_TREADY	in	1	axis	ost_V	pointer