// (C) Tomonori Izumi <izumi@ieee.org>, Feb. 2014. All rigts reserved.

// block RAM model : 1port ,pipelined

// parameter DW ... data bitwidth
// parameter AW ... addr bitwidth
// parameter SZ ... memory size (i.e. 2^AW)

// a experimental synthesis of 8bit*4096word memory (2014.2.28)
// Xilinx XC5VLX30+ISE
// no   delay ... 172 slices, 0 BRAM(36k)
// 1cyc delay ...  10 slices, 1 BRAM(36k)
// 2cyc delay ...  10 slices, 1 BRAM(36k)
// Altera EP4CE115+Quartus II
// no   delay ... 46043 LEs,     0 mem bits
// 1cyc delay ...    99 LEs, 32768 mem bits
// 2cyc delay ...    65 LEs, 32768 mem bits


// no delay ... only for small memory!
module mem0pipe_module(clk, a, d, q, we);
   parameter DW = 8;
   parameter AW = 3;
   parameter SZ = 8;

   input     clk, we;
   input [AW-1:0] a;
   input [DW-1:0] d;
   output [DW-1:0] q;

   reg [DW-1:0]    mem[SZ-1:0];
   
   always @(posedge clk)
     begin
	if (we) begin
	   mem[a]<=d;
	end
     end

   assign q = mem[a];

endmodule


// 1 cycle delay
module mem1pipe_module(clk, a, d, q, we);
   parameter DW = 8;
   parameter AW = 3;
   parameter SZ = 8;

   input     clk, we;
   input [AW-1:0] a;
   input [DW-1:0] d;
   output [DW-1:0] q;

   reg [AW-1:0]    a_reg;
   reg [DW-1:0]    d_reg;
   reg 		   we_reg;
   
   reg [DW-1:0]    mem[SZ-1:0];
   
   always @(posedge clk)
     begin
	a_reg<=a;
	d_reg<=d;
	we_reg<=we;
     end

   always @(posedge clk)
     begin
	if (we_reg) begin
	   mem[a_reg]<=d_reg;
	end
     end

   assign q = mem[a_reg];

endmodule


// 2cycles delay
module mem2pipe_module(clk, a, d, q, we);
   parameter DW = 8;
   parameter AW = 3;
   parameter SZ = 8;

   input     clk, we;
   input [AW-1:0] a;
   input [DW-1:0] d;
   output [DW-1:0] q;

   reg [AW-1:0]    a_reg;
   reg [DW-1:0]    d_reg;
   reg 		   we_reg;
   reg [DW-1:0]    q_reg;
   
   reg [DW-1:0]    mem[SZ-1:0];
   
   always @(posedge clk)
     begin
	a_reg<=a;
	d_reg<=d;
	we_reg<=we;
     end

   always @(posedge clk)
     begin
	if (we_reg) begin
	   mem[a_reg]<=d_reg;
	   q_reg<=mem[a_reg];
	end else begin
	   q_reg<=mem[a_reg];
	end
     end

   assign q = q_reg;

endmodule