Synthesis Report for 'hls_macc'

General Information

Date: Tue Oct 06 14:32:10 2015
Version: 2015.2 (Build 1266856 on Fri Jun 26 16:57:37 PM 2015)
Project: vhls_prj
Solution: solution1
Product family: zynq
Target device: xc7z010clg400-1

Performance Estimates

Timing (ns)
- Summary

Clock	Target	Estimated	Uncertainty
ap_clk	10.00	8.52	1.25

Latency (clock cycles)
- Summary
- Detail
  - Instance
  - Loop

Latency	Interval	Type
min	max	min	max
6	6	7	7	none

Utilization Estimates

Summary

Name	BRAM_18K	DSP48E	FF	LUT
Expression	-	-	0	64
FIFO	-	-	-	-
Instance	0	4	157	234
Memory	-	-	-	-
Multiplexer	-	-	-	2
Register	-	-	72	-
Total	0	4	229	300
Available	120	80	35200	17600
Utilization (%)	0	5	~0	1

Detail
- Instance
- Memory
- FIFO
- Expression
- Multiplexer
- Register

Instance	Module	DSP48E	FF	LUT
hls_macc_HLS_MACC_PERIPH_BUS_s_axi_U	hls_macc_HLS_MACC_PERIPH_BUS_s_axi	0	157	234
hls_macc_mul_32s_32s_32_6_U0	hls_macc_mul_32s_32s_32_6	4	0	0
Total	2	4	157	234

Variable Name	Operation	LUT	Bitwidth P0	Bitwidth P1
tmp_2_fu_74_p2	+	32	32	32
p_acc_reg_load_fu_67_p3	Select	32	1	1
Total	2	64	33	33

Name	LUT	Input Size	Bits	Total Bits
ap_NS_fsm	2	8	1	8
Total	2	8	1	8

Name	FF	Bits
acc_reg	32	32
accum_clr_read_reg_86	1	1
ap_CS_fsm	7	7
tmp_2_reg_101	32	32
Total	72	72

Interface

Summary

RTL Ports	Dir	Bits	Protocol	Source Object	C Type
s_axi_HLS_MACC_PERIPH_BUS_AWVALID	in	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_AWREADY	out	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_AWADDR	in	6	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_WVALID	in	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_WREADY	out	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_WDATA	in	32	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_WSTRB	in	4	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_ARVALID	in	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_ARREADY	out	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_ARADDR	in	6	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_RVALID	out	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_RREADY	in	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_RDATA	out	32	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_RRESP	out	2	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_BVALID	out	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_BREADY	in	1	s_axi	HLS_MACC_PERIPH_BUS	scalar
s_axi_HLS_MACC_PERIPH_BUS_BRESP	out	2	s_axi	HLS_MACC_PERIPH_BUS	scalar
ap_clk	in	1	ap_ctrl_hs	hls_macc	return value
ap_rst_n	in	1	ap_ctrl_hs	hls_macc	return value
interrupt	out	1	ap_ctrl_hs	hls_macc	return value