Synthesis Report for 'hls_xfft2real'

General Information

Performance Estimates

• Timing (ns)
  
  
  • Summary
    
    

    Clock	Target	Estimated	Uncertainty
    ap_clk	4.00	5.42	0.50

• Latency (clock cycles)
  
  
  • Summary
    
    

    Latency		Interval		Type
    min	max	min	max
    3073	8194	2562	7682	dataflow

  • Detail
    
    
    • Instance
      
      

      Instance	Module	Latency		Interval		Type
      		min	max	min	max
      grp_hls_xfft2real_Loop_realfft_be_buffer_proc_fu_64	hls_xfft2real_Loop_realfft_be_buffer_proc	511	512	511	512	none
      grp_hls_xfft2real_Loop_realfft_be_descramble_pro_fu_50	hls_xfft2real_Loop_realfft_be_descramble_pro	2561	7681	2561	7681	none

    • Loop
      
      

      N/A

Utilization Estimates

• Summary
  
  

  Name	BRAM_18K	DSP48E	FF	LUT
  Expression	-	-	0	1
  FIFO	-	-	-	-
  Instance	2	4	760	586
  Memory	8	-	0	0
  Multiplexer	-	-	-	8
  Register	-	-	7	-
  Total	10	4	767	595
  Available	280	220	106400	53200
  Utilization (%)	3	1	~0	1

• Detail
  
  
  • Instance
    
    

    Instance	Module	BRAM_18K	DSP48E	FF	LUT
    hls_xfft2real_Loop_realfft_be_buffer_proc_U0	hls_xfft2real_Loop_realfft_be_buffer_proc	0	0	12	24
    hls_xfft2real_Loop_realfft_be_descramble_pro_U0	hls_xfft2real_Loop_realfft_be_descramble_pro	2	4	748	562
    Total	2	2	4	760	586

  • Memory
    
    

    Memory	Module	BRAM_18K	FF	LUT	Words	Bits	Banks	W*Bits*Banks
    descramble_buf_0_M_real_V_U	hls_xfft2real_descramble_buf_0_M_real_V	2	0	0	256	16	2	8192
    descramble_buf_1_M_real_V_U	hls_xfft2real_descramble_buf_0_M_real_V	2	0	0	256	16	2	8192
    descramble_buf_0_M_imag_V_U	hls_xfft2real_descramble_buf_0_M_real_V	2	0	0	256	16	2	8192
    descramble_buf_1_M_imag_V_U	hls_xfft2real_descramble_buf_0_M_real_V	2	0	0	256	16	2	8192
    Total	4	8	0	0	1024	64	8	32768

  • FIFO
    
    

    N/A

  • Expression
    
    

    Variable Name	Operation	DSP48E	FF	LUT	Bitwidth P0	Bitwidth P1
    hls_xfft2real_Loop_realfft_be_descramble_pro_U0_ap_start	and	0	0	1	1	1
    Total	1	0	0	1	1	1

  • Multiplexer
    
    

    Name	LUT	Input Size	Bits	Total Bits
    ap_chn_write_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_imag_V	1	2	1	2
    ap_chn_write_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_real_V	1	2	1	2
    ap_chn_write_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_imag_V	1	2	1	2
    ap_chn_write_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_real_V	1	2	1	2
    ap_sig_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_imag_V_pipo_status	1	2	1	2
    ap_sig_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_real_V_pipo_status	1	2	1	2
    ap_sig_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_imag_V_pipo_status	1	2	1	2
    ap_sig_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_real_V_pipo_status	1	2	1	2
    Total	8	16	8	16

  • Register
    
    

    Name	FF	LUT	Bits	Const Bits
    ap_CS	1	0	1	0
    ap_reg_procdone_hls_xfft2real_Loop_realfft_be_buffer_proc_U0	1	0	1	0
    ap_reg_procdone_hls_xfft2real_Loop_realfft_be_descramble_pro_U0	1	0	1	0
    ap_reg_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_imag_V_pipo_status	1	0	1	0
    ap_reg_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_0_M_real_V_pipo_status	1	0	1	0
    ap_reg_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_imag_V_pipo_status	1	0	1	0
    ap_reg_ready_hls_xfft2real_Loop_realfft_be_buffer_proc_U0_descramble_buf_1_M_real_V_pipo_status	1	0	1	0
    Total	7	0	7	0

Interface

• Summary
  
  

  RTL Ports	Dir	Bits	Protocol	Source Object	C Type
  ap_clk	in	1	ap_ctrl_hs	hls_xfft2real	return value
  ap_rst_n	in	1	ap_ctrl_hs	hls_xfft2real	return value
  ap_done	out	1	ap_ctrl_hs	hls_xfft2real	return value
  ap_start	in	1	ap_ctrl_hs	hls_xfft2real	return value
  ap_idle	out	1	ap_ctrl_hs	hls_xfft2real	return value
  ap_ready	out	1	ap_ctrl_hs	hls_xfft2real	return value
  din_TDATA	in	32	axis	din_V_data	pointer
  din_TLAST	in	1	axis	din_V_last_V	pointer
  din_TVALID	in	1	axis	din_V_last_V	pointer
  din_TREADY	out	1	axis	din_V_last_V	pointer
  dout_V_TDATA	out	32	axis	dout_V	pointer
  dout_V_TVALID	out	1	axis	dout_V	pointer
  dout_V_TREADY	in	1	axis	dout_V	pointer