// (C) Tomonori Izumi , Oct. 2025 module counter_module(xreset, clock, run, count); input wire xreset; input wire clock; input wire run; output reg [7:0] count; always @(posedge clock or negedge xreset) begin if (!xreset) begin count <= 0; end else begin if (run) begin count <= count + 1; end else begin count <= 0; end end end endmodule