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| 2008 | |
| (1) |
道関隆国、 “バッテリレスシステムのセンサネットワークへの応用”、独立行政法人科学技術振興機構『希薄分散エネルギー活用技術』に関する科学技術未来戦略ワークショップ報告書pp. 50-55, March 2008. |
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| (2) |
S. Sasaki, T.Douseki, Y. Matsuya, “Batteryless Optical Wireless Audio Receiver Uses 1-Bit ΣΔ-Modulated Visible Light and Spherical Si Solar Cells,” SICE Annual Conference 2008, pp. 1264-1268, Aug. 2008. |
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| (3) |
Yoshifumi Yoshida, Fumiyasu Utsunomiya, Takauni Douseki, “Ultralow-voltage, Smart DC-DC Converter for Thermoelectrically Powered Wristwatch, ” ECS, PRiME2008、Oct. 2008. |
|
| (4) |
T. Douseki, S. Sasaki, Y. Matsuya, “Optical-wireless Digital-sound Transmission System With Spherical Solar Cells”, IEEE SENSORS 2008, pp. 608-611, Oct. 2008. |
| 2006-2007 | |
| (1) |
N. Shibata, H. Kiya, S. Kurita, H. Okamoto, M. Tan’no, and T. Douseki, “A 0.5-V
25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable
Personal Digital Equipment- Sure Write Operation by Using Step-Down Negatively
Overdriven Bitline Scheme,” IEEE J. Solid-state Circuits, Vol. 41, No. 3, pp. 728-742, March 2006.
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| (2) |
T. Sakurai, A. Matsuzawa, and T. Douseki, “Fully-Depleted SOI CMOS Circuits and Technology for Ultra-Low-Power Applications,” ISBN-10 0-387-29217-9, Springer, Apr. 2006.
|
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| (3) |
門勇一、道関隆国、松谷康之、束原恒夫、“極低電力CMOS/SOI回路技術”、電気
学会論文誌C、IEEJ Trans. EIS, Vol. 126, No.6, pp.725-729, June 2006.
|
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| (4) |
Y. Yoshida, F. Utsunomiya, and T. Douseki, “Adaptive-Vth CMOS/SOI DC-DC
Converter Scheme,” 2006 IEEE International SOI Conference, pp. 119-120,
Oct. 2006.
|
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| (5) |
道関隆国、 “バッテリレスシステムに向けた極低電力LSI 技術”、SEAJ/SEMI
Industry Strategy and Technology Forum 2006, Oct. 2006.
|
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| (6) |
道関隆国、 “ユビキタスエネルギー源”、日本学術振興会『ワイヤレス・センサーネ
ットワーク社会に向けたナノメートルCMOSシステムとその要素技術の研究』に関す
る先導的研究開発委員会報告書pp. 44-47, pp.105-106, March 2007.
|
| 1987-2005 | |
| [1]学術論文 |
| (1) |
道関隆国、大森康生、“BiCMOS技術による大容量・高速SRAMの構成法”
電子情報通信学会論文誌、C、Vol. J70-C, No.6, pp.783-790, June 1987.
|
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| (2) |
T. Douseki and Y. Ohmori, “BiCMOS Circuit Technology for a High-Speed SRAM,”
IEEE J. solid-state Circuits, Vol. 23, No. 1, pp. 68-73, Feb. 1988.
|
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| (3) |
T. Douseki, Y. Ohmori, H. Yoshino, and J. Yamada, “Fast-Access BiCMOS SRAM
with a VSS Generator,” IEEE J. Solid-State Circuits, Vol. 24, No. 4, pp. 513-517,
Apr. 1991.
|
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| (4) |
道関隆国、大森康生, “パイポーラ論理回路を用いた高速・大容量BiCMOS SRAM
の構成法” 電子情報通信学会論文誌、C-II、Vol. J74-C-II, No.9, pp. 690-699,
Sep. 1991.
|
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| (5) |
M. Tanimoto, T. Douseki, and T. Takigami, “An Analysis of p+-n Junction
Capacitance with Three-Dimensional Impurity Profiling Method Using Scanning
Tunneling Microscopy.” Japanese Journal of Applied Physics, Vol. 30, No. 12B,
pp. 3638-3641, Dec. 1991.
|
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| (6) |
道関隆国、武藤伸一郎、”微細CMOSメモリセルのスタティックノイズマージン解析”、
電子情報通信学会論文誌、C-II、Vol. J75-C-II, No.7, pp. 350-361, July 1992.
|
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| (7) |
T. Douseki, T. Nagayama, and Y. Ohmori, “A Bipolar Divided Word-Line Scheme for
a High-Speed and Large-Capacity BiCMOS SRAM.” Trans. IEICE, Vol. E75-C,
No. 11, pp. 1364-1368, Nov. 1992.
|
|
| (8) |
T. Douseki and S. Mutoh, “A High-Speed Feed-Forward BiNMOS Driver for Low
Voltage LSIs.” Trans. IEICE, Vol. E76-C, No. 5, pp. 687-694, May 1993.
|
|
| (9) |
T. Douseki, K. Aoyama, and Y. Omura, “Dependence of CMOS/SIMOX Inverter Delay
Time on Gate Overlap Capacitance,” Trans. IEICE, Vol. E76-C, No. 8, pp. 1325-1332,
Aug. 1993.
|
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| (10) |
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V
Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage
CMOS,” IEEE J. Solid-State Circuits, Vol. 30, No. 8, pp. 847-854, Aug. 1995.
|
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| (11) |
T. Douseki, S. Mutoh, T. Ueki, and J. Yamada, “Evaluation of Soft-Error Immunity for
1-V CMOS Memory Cells with MTCMOS Technology.” Trans. IEICE, Vol. E79-C,
No. 2, pp. 179-184, Feb. 1996.
|
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| (12) |
T. Douseki and S. Mutoh, “A 1-V MTCMOS Circuit Hardened to Temperature-
Dependent Delay-Time Variation,” Trans. IEICE, Vol. E79-C, No. 8, pp. 1131-11136,
Aug. 1996.
|
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| (13) |
T. Douseki, M. Harada, and T. Tsuchiya, “Ultra-Low-Voltage MTCMOS/SIMOX
Technology Hardened to Temperature Variation,” Solid-State Electronics, Vol. 41,
No. 4, pp. 519-525, Feb. 1997.
|
|
| (14) |
T. Douseki, S.Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchiya, “A
0.5-V MTCMOS/SIMOX Logic Gate,” IEEE J. Solid-State Circuits, Vol. 32, No. 10,
pp. 1604-1609, Oct. 1997.
|
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| (15) |
T. Douseki, T. Shimamura, K. Fujii, and J. Yamada, “Energy-Reduction Effect of
Ultralow-Voltage MTCMOS/SIMOX Circuits Using a Graph with Equispeed and
Equienergy Lines,” Trans. IEICE, Vol. E83-C, No. 2, pp. 212-219, Feb. 2000.
|
|
| (16) |
S. Nakata, T. Douseki, Y. Kado, and J. Yamada, “A Low Power Multiplier Using
Adiabatic Charging Binary Decision Diagram Circuit,” Jpn. J. Appl. Phys. Vol. 39,
pp. 2305-2311, Part 1, No. 4B, April 2000.
|
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| (17) |
T. Douseki, T. Yamada, J. Yamada, K. Ito, and K. Nishi, “Photovoltaic Display Module
in a Mobile GPS,” Solar Energy Materials & Solar Cells, Vol 67, pp. 543-549, 2001.
|
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| (18) |
K. Fujii and T. Douseki, “A Sub-1V Bootstrap Pass-Transistor Logic,” Trans. IEICE,
Vol. E86-C, No. 4, pp. 604-611, Apr. 2003.
|
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| (19) |
J. Kodate, M. Ugajin, T. Tsukahara, T. Douseki, N. Sato, T. Okaba, K. Ohmi, and
T. Yonehara, “Gain Improvement of a 2.4-GHz/5GHz CMOS Low Noise Amplifier by
Using High-ResistivitySilicon-on-Insulator,” Trans. IEICE, Vol. E86-C, No. 6,
pp. 1041-1049, June 2003.
|
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| (20) |
T. Douseki, M. Yonemaru, E. Ikuta, A. Matsuzawa, A. Kameyama, S. Baba, T. Mogami,
and H. Kyuragi, “Ultralow-voltage MTCMOS/SOI Circuits for Batteryless Mobile
System,” Trans. IEICE, Vol. E87-C, No. 4, pp. 437-447, April 2004.
|
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| (21) |
Y. Yoshida, F. Utsunomiya, and T. Douseki, “Sub-1-V Power-supply System with
Variable-stage SC-type DC-DC Converter Scheme for Ambient Energy Sources,”
Trans. IEICE, Vol. E88-C, No. 4, pp. 484-489, April 2005.
|
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| (22) |
T. Douseki, T. Shimamura, and N. Shibata, “A Sub-0.5V Differential ED-CMOS/SOI
Circuit with Over-1-GHz Operation,” Trans. IEICE, Vol. E88-C, No. 4, pp. 582-588,
April 2005.
|
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| (23) |
J. Kodate, T. Douseki, T. Tsukahara, T. Okabe, and N. Sato, “Practical High-
Resistivity Silicon-on-Insulator Solution for Spiral Inductors in CMOS RFICs, “
Jpn. J. Apply. Phys., Vol. 44 (2005), No. 8, pp. 5987-5993, 2005.
|
| [2] 国際会議 |
| (1) |
T. Douseki and Y. Ohmori, “BiCMOS Circuit Technology for a High-Speed SRAM,”
1987 Symp. VLSI Circuits, pp. 77-78, May. 1987.
|
|
| (2) |
T. Douseki, Y. Ohmori, H. Yoshino, and J. Yamada, “Fast-Access BiCMOS SRAM
with a VSS Generator,” 1990 Symp. VLSI Circuits, pp. 45-46, June. 1990.
|
|
| (3) |
M. Tanimoto, T. Douseki, and T. Takigami, “An Analysis of p+-n Junction
Capacitance with Three-Dimensional Impurity Profiling Method Using Scanning
Tunneling Microscopy,” The 1991 International Conference on Solid State Device
and Materials, pp. 50-52, Aug. 1991.
|
|
| (4) |
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1-V High-Speed Digital
Circuit Technology with 0.5-mm Multi-threshold CMOS,” Sixth Annual IEEE
International ASIC Conference and Exhibit, pp. 186-189, Sep. 1993.
|
|
| (5) |
T. Douseki, S. Mutoh, T. Ueki, and J. Yamada, “Soft-Error Immunity of 1-Volt CMOS
Memory Cells with MTCMOS Technology,” The 1995 International Conference on
Microelectonic Test Structure, pp. 107-111, Mar. 1995.
|
|
| (6) |
T. Douseki, S.Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, and T. Tsuchiya, “A
0.5-V SIMOX-MTCMOS Circuit with 200 ps Logic Gate,” 1996 IEEE International
Solid-State Circuits Conference, pp. 84-85, Feb. 1996
|
|
| (7) |
T. Douseki, Y. Tanabe, M. Harada and T. Tsuchiya, “A 0.5-V MTCMOS/SIMOX
Data-Storage Circuit for Power-Down Applications,” The 8th International
Symposium on Silicon-On-Insulator Technology and Devices, pp. 378-383,
Aug. 1997.
|
|
| (8) |
M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, and T. Tsuchiya, “An Ultra-
Low-Voltage MTCMOS/SIMOX Gate Array,” Tenth Annual IEEE International ASIC
Conference and Exhibit, pp. 7-11, Sep. 1997.
|
|
| (9) |
K. Fujii, T. Douseki, and M. Harada, “A Sub-1V Triple-Threshold CMOS/SIMOX
Circuit for Active Power Reduction,” 1998 IEEE International Solid-State Circuits
Conference, pp. 190-191, Feb. 1998.
|
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| (10) |
T. Douseki and J. Yamada, “Sub-1V MTCMOS/SIMOX Circuit Technology,”
The1998 International Conference on Solid State Device and Materials, pp. 308-309,
Aug. 1998.
|
|
| (11) |
T. Douseki and M. Harada, “A 0.5-V Data-Storage Circuit for Triple-Threshold
MTCMOS/SIMOX LSIs,” 1998 IEEE International SOI Conference, pp. 117-118,
Oct. 1998.
|
|
| (12) |
T. Douseki and J. Yamada, “MTCMOS/SIMOX Circuit Technology for Sub-1V LSIs,”
The 9th International Symposium on Silicon-On-Insulator Technology and Devices,
pp. 311-322, May. 1999.
|
|
| (13) |
T. Douseki, T. Yamada, J. Yamada, K. Ito, and K. Nishi, “Photovoltaic Display Module
in a Mobile GPS,” 11-th International Photovoltaic Science and Engineering
Conference, pp. 245-246, 1999.
|
|
| (14) |
K. Fujii and T. Douseki, “A 0.5-V, 3-mW, 54x54-b Multiplier with a Triple-Vth
CMOS/SIMOX Circuit Scheme,” 2000 IEEE International SOI Conference, pp. 24-25,
Oct. 2000.
|
|
| (15) |
T. Douseki, N. Shibata, and J. Yamada, “A 0.5-1V MTCMOS/SIMOX SRAM Macro
With Multi-Vth Memory Cells,” 2000 IEEE International SOI Conference, pp. 24-25,
Oct. 2000.
|
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| (16) |
T. Douseki, “Ultralow-Voltage MTCMOS/SIMOX Circuit Technology,” Proc. of 3rd
International Symposium on Advance and Technology of Silicon Materials,
pp.667-675, Nov. 2000.
|
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| (17) |
K. Fujii, T. Douseki and Y. Kado, “A Sub-1V Dual-Threshold Domino Circuit Using
Product-of-Sum Logic,” Proc. 2001 International Symposium on Low Power
Electronics and Design, pp.259-262, Aug. 2001.
|
|
| (18) |
T. Douseki and J. Yamada, “Low Voltage SOI Circuit Technology,” 2001 International
Conference on Solid State Device and Materials, pp.258-259, Sep. 2001.
(Invited Paper)
|
|
| (19) |
T. Douseki, F. Morisawa, S. Nakata, and Y. Ohtomo, “A 0.5-V, Over 1-GHz, 1-mW
MUX/DEMUX Core with Multi-Threshold Zero-Vth CMOS/SIMOX Technology,”
2001 International Conference on Solid State Device and Materials, pp. 264-265,
Sep. 2001.
|
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| (20) |
T. Douseki, “Ultralow-voltage Multi-Vth CMOS/SOI Circuit Technology,” Extended
Abstracts of International Symposium on Advanced CMOS Devices, pp. 29-32,
Oct. 2001.
(Invited Paper)
|
|
| (21) |
T. Douseki, N. Shibata, and J. Yamada, “A 0.5-1V MTCMOS/SIMOX ROM Macro
with Low-Vth Memory Cells,” 2001 IEEE International SOI Conference, pp. 143-144,
Oct. 2001.
|
|
| (22) |
J. Kodate, M. Ugajin, T. Tsukahara, T. Douseki, N. Sato, T. Okabe, K. Ohmi, and T.
Yonehara, “A 2.4-GHz/5-GHz CMOS low noise amplifier with high-resistivity
ELTRAN@ SOI-Epi wafers,” 2002 IEEE MTT-S Int. Microwave Symp. Dig., Vol. 3,
pp. 1419-1422, May 2002.
|
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| (23) |
T. Douseki, J. Yamada, and H. Kyuragi, “Ultralow-power CMOS/SOI LSI Design for
Future Mobile Systsms,” 2002 IEEE Symposium on VLSI Circuits, Digest of
Technical Papers, pp. 6-9, June 2002.
(Invited Paper, Plenary Talk)
|
|
| (24) |
N. Hama, A. Yajima, Y. Yoshida, F. Utsunomiya, J. Kodate, T. Tsukahara, and
T. Douseki, “SOI Circuit Technology for Batteryless Mobile System with Green
Energy Sources,” 2002 IEEE Symposium on VLSI Circuits, Digest of Technical
Papers, pp. 280-283, June 2002.
|
|
| (25) |
T. Douseki, T. Shimamura, and N. Shibata, “A 0.3 V 3.6 GHz 0.3mW Frequency
Divider with Differential ED-CMOS/SOI Circuit Technology,” 2003 IEEE
International Solid-State Circuits Conference, pp. 114-115, Feb. 2003.
|
|
| (26) |
T. Douseki, Y. Yoshida, F. Utsunomiya, and N. Hama, “A Batteryless Wireless System
Uses Ambient Heat with a Reversible-Power-Source Compatible CMOS/SOI
DC-DC Converter,” 2003 IEEE International Solid-State Circuits Conference,
pp. 388-389, Feb. 2003.
|
|
| (27) |
T. Douseki and H. Kyuragi, “Ultralow-power FD-SOI design for future mobile
systems,” The 11th International Symposium on Silicon-On-Insulator Technology
and Devices, pp. 209-214, May. 2003.
(Invited Paper)
|
|
| (28) |
Y. kado, Y. Matsuya, S. Mutoh, J. Terada, H. Morisawa, Y. Sato, T. Douseki, and H.
Kyuragi, “Ultralow-power CMOS/SOI Circuit Technology for Ubiquitous
Communications,” 2003 International Conference on Solid State Device and
Materials, pp. 746-747, Sep. 2003.
(Invited Paper)
|
|
| (29) |
H. Matsuhashi, T. Okamura, T. Douseki, N. Miura, T. Chiba, and S. Baba, “On the
Performance Advantage of undoped ultra thin-film FD-SOI MOSFETs,” 2003
International Conference on Solid State Device and Materials, pp. 748-749,
Sep. 2003.
|
|
| (30) |
Y. Matsuya and T. Douseki, “A 0.5-V Noise-Shaping A/D Converter Using Low-
Threshold FD-SOI Transistors,” 2003 International Conference on Solid State
Device and Materials, pp. 750-751, Sep. 2003.
|
|
| (31) |
T. Douseki, T. Tsukahara, Y. Yoshida, F. Utsunomiya, and N. Hama, “A Batteryless
Wireless System with MTCMOS/SOI Circuit Technology,” IEEE Custom Integrated
Circuits Conference 2003, pp. 163-167, Sep. 2003.
(Invited Paper)
|
|
| (32) |
T. Douseki and H. Kyuragi, “Ultralow-voltage MTCMOS/SOI Circuits for Batteryless
Wireless System,” 2003 IEEE International SOI Conference, pp. 5-8, Sep. 2003.
(Invited Paper)
|
|
| (33) |
T. Douseki, “A Batteryless Optical-Wireless System with White-LED Illumination
2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio
Communications, p. 2529-2533, Sep. 2004.
|
|
| (34) |
T. Douseki, “Ultralow-voltage MTCMOS/SOI Technology for Batteryless Mobile
System,” The 7th 2003 International Conference on Solid-State and Integrated-
Circuit Technology,” pp. 1242-1247, Oct. 2004.
|