(C) 2017, 2018 by T.Izumi   ver.2018.8.23

Hello world in Verilog  /  Verilog で Hello world

Displaying "Hello world" is the first code to be written by a beginer who starts to learn the progrmming language. So, here is a sample code written in Verilog to display "Hello world".

プログラミング言語を勉強する初心者が最初に書くのが“Hello world”を表示するプログラム。なので、Verilogで“Hello world”を表示するコードを書いてみた。

Izumi Lab, Dept. Elec.&Comp. Eng., Ritsumeikan Univ.


Target Boards and Tools

FPGA board ZYBO ZYBO Z7 020 + Pmod VGA
connect Pmod VGA to
JD and JE on ZYBO Z7
Nexys4
tools testedVivado 2016.4Vivado 2017.4Vivado 2017.4

0. Setup

boardfiles
install boardfiles:
https://reference.digilentinc.com/vivado:boardfiles
Source Codes
extract sample source codes:
HelloVerilog.zip

1. Launch Vivado

2. Create Project

3. Add Files

4. Build

5. Program FPGA

6. Check "Hello world"


Source Codes

hello_vga.v (excerpted)

// (C) Tomonori Izumi , Nov. 2017. All rigts reserved.

module hello_vga(P,HS,VS,clk);
   
   // 640*480, Pixel 25.175MHz, Horiz 31.46875kHz, Verti 59.94Hz
   parameter Pcount_W  =    5; // 39.722ns = 4.965clocks@125MHz
   parameter Hcount_W  = 3972; // H width       800 pix  3972clk
   parameter Hactive_H =    0; // H display     640 pix     0-3176
   parameter Hactive_L = 3177; // H front porch  16 pix  3177-3256
   parameter Hpulse_L  = 3257; // H pulse(neg)   96 pix  3257-3733
   parameter Hpulse_H  = 3734; // H back porch   48 pix  3734-3971
   parameter Vcount_W  =  525; // V width       525 lines
   parameter Vactive_H =    0; // V display     480 lines   0-479
   parameter Vactive_L =  480; // V front porch  10 lines 480-489
   parameter Vpulse_L  =  490; // V pulse(neg)    2 lines 490-491
   parameter Vpulse_H  =  492; // V back porch   33 lines 492-524
   
   output    reg  P=0;
   output    reg  HS=1,VS=1;
   input     wire clk;

   reg [11:0] Hcount=0;
   reg [9:0]  Vcount=0;

   // Horizontal&Vertical counters
   always @(posedge clk)
     if (Hcount<Hcount_W-1) begin
	Hcount<=Hcount+1;
     end else if (Vcount<Vcount_W-1) begin
	Hcount<=0;
	Vcount<=Vcount+1;
     end else begin
	Hcount<=0;
	Vcount<=0;
     end

   // Horizontal&Vertical sync pulses
   always @(posedge clk) begin
     case (Hcount)
       Hpulse_L: HS<=0;
       Hpulse_H: HS<=1;
     endcase
     case (Vcount)
       Vpulse_L: VS<=0;
       Vpulse_H: VS<=1;
     endcase
   end

   // Hello World
   function [6:0] tbl;
   input [9:0] col;
   case (col)
      0: tbl=7'b1111111;
      1: tbl=7'b0001000;
      2: tbl=7'b0001000;
      3: tbl=7'b0001000;
      4: tbl=7'b1111111;
      5: tbl=7'b0000000;
      6: tbl=7'b0111000;
      7: tbl=7'b1010100;
      8: tbl=7'b1010100;
      9: tbl=7'b1010100;
     10: tbl=7'b0011000;
     11: tbl=7'b0000000;
     12: tbl=7'b1111111;
     13: tbl=7'b0000000;
     14: tbl=7'b1111111;
     15: tbl=7'b0000000;
     16: tbl=7'b0111000;
     17: tbl=7'b1000100;
     18: tbl=7'b1000100;
     19: tbl=7'b1000100;
     20: tbl=7'b0111000;
     21: tbl=7'b0000000;
     22: tbl=7'b0000000;
     23: tbl=7'b0000000;
     24: tbl=7'b0111100;
     25: tbl=7'b1000000;
     26: tbl=7'b0111100;
     27: tbl=7'b1000000;
     28: tbl=7'b0111100;
     29: tbl=7'b0000000;
     30: tbl=7'b0111000;
     31: tbl=7'b1000100;
     32: tbl=7'b1000100;
     33: tbl=7'b1000100;
     34: tbl=7'b0111000;
     35: tbl=7'b0000000;
     36: tbl=7'b1111100;
     37: tbl=7'b0001000;
     38: tbl=7'b0000100;
     39: tbl=7'b0000100;
     40: tbl=7'b0001000;
     41: tbl=7'b0000000;
     42: tbl=7'b1111111;
     43: tbl=7'b0000000;
     44: tbl=7'b0111000;
     45: tbl=7'b1000100;
     46: tbl=7'b1000100;
     47: tbl=7'b0101000;
     48: tbl=7'b1111111;
     default: tbl=0;
   endcase
   endfunction

   function [6:0] rowdec;
   input [9:0] row;
   case (row)
     0:rowdec=7'b0000001;
     1:rowdec=7'b0000010;
     2:rowdec=7'b0000100;
     3:rowdec=7'b0001000;
     4:rowdec=7'b0010000;
     5:rowdec=7'b0100000;
     6:rowdec=7'b1000000;
     default: rowdec=0;
   endcase
   endfunction
   
   always @(posedge clk)
     if (Hcount<Hactive_L && Vcount<Vactive_L)
       P<=(tbl(Hcount[11:4])&rowdec(Vcount[9:1]))?1:0;
     else
       P<=0;
   
endmodule

zybo_top.v (excerpted)

// (C) Tomonori Izumi , Nov. 2017. All rigts reserved.

module ZYBO_top
  (CLK125M, vga_r, vga_g, vga_b, vga_hs, vga_vs);
   input  wire        CLK125M;
   output wire [4:0]  vga_r;
   output wire [5:0]  vga_g;
   output wire [4:0]  vga_b;
   output wire        vga_hs,vga_vs;

   wire   CLK125M_ibuf,clk;
   IBUFG ibuf_clk(.I(CLK125M), .O(CLK125M_ibuf));
   BUFG  buf_clk(.I(CLK125M_ibuf),.O(clk));

   wire   vga_p;
   hello_vga hello_vga_0(vga_p,vga_hs,vga_vs,clk);
   assign vga_r=(vga_p==0)?0:5'h1f;
   assign vga_g=(vga_p==0)?0:6'h3f;
   assign vga_b=(vga_p==0)?0:5'h1f;

endmodule

zybo.xdc (excerpted)

# parts XC7Z010-1CLG400C

##Clock signal
#IO_L11P_T1_SRCC_35
set_property PACKAGE_PIN L16 [get_ports CLK125M]
set_property IOSTANDARD LVCMOS33 [get_ports CLK125M]
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports CLK125M]

##VGA Connector
set_property PACKAGE_PIN M19 [get_ports {vga_r[0]}]
set_property PACKAGE_PIN L20 [get_ports {vga_r[1]}]
set_property PACKAGE_PIN J20 [get_ports {vga_r[2]}]
set_property PACKAGE_PIN G20 [get_ports {vga_r[3]}]
set_property PACKAGE_PIN F19 [get_ports {vga_r[4]}]
set_property PACKAGE_PIN H18 [get_ports {vga_g[0]}]
set_property PACKAGE_PIN N20 [get_ports {vga_g[1]}]
set_property PACKAGE_PIN L19 [get_ports {vga_g[2]}]
set_property PACKAGE_PIN J19 [get_ports {vga_g[3]}]
set_property PACKAGE_PIN H20 [get_ports {vga_g[4]}]
set_property PACKAGE_PIN F20 [get_ports {vga_g[5]}]
set_property PACKAGE_PIN P20 [get_ports {vga_b[0]}]
set_property PACKAGE_PIN M20 [get_ports {vga_b[1]}]
set_property PACKAGE_PIN K19 [get_ports {vga_b[2]}]
set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}]
set_property PACKAGE_PIN G19 [get_ports {vga_b[4]}]
set_property PACKAGE_PIN P19 [get_ports vga_hs]
set_property PACKAGE_PIN R19 [get_ports vga_vs]

set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports vga_hs]
set_property IOSTANDARD LVCMOS33 [get_ports vga_vs]


泉 知論立命館大学 理工学部 電子情報工学科
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