Copyright (C) 2022, Tomonori IZUMI, Reconfigurable Sysems Lab @ Ritsumeikan U, All rights reserved.

Random Number Generators for FPGAs


This site provides template codes of random number generators for FPGAs, utilizing High-Level Synthesis.

Design Policy

  • Be simple!
  • Just outputs random numbers
  • Output as stream
  • No start/done controls
  • Seed is embedded in the code
  • Initialized by the bitstream
  • Readable and portable code
 

Source Codes for Vitis HLS

Linear Congruential Generator (LCG)

Linear Feedback Shift Register (LFSR)

Combined Tausworthe (TW)

Mersenne Twister (MT)

Testbench

Performance and Resource Usage

Speed and Resource Usage of the random number generators evaluated with Vitis HLS 2020.2 and Vivado 2020.2, targeted to xc7z010-clg400-1, 10.00ns.
source code Vitis HLS Synthesis estimate Vivado Synthesis estimate
Timing Latency Interval BRAM DSP FF LUT BRAM DSP FF LUT
LCG.cpp 6.912 ns 3 clocks 2 clocks 0 0 232 129 0 3 152 75
LFSR_orig.cpp 0.992 ns 1 clock 1 clock 0 0 34 78 0 0 101 25
LFSR.cpp 0.992 ns 1 clock 1 clock 0 0 34 78 0 0 101 25
TW_orig.cpp 1.986 ns 1 clock 1 clock 0 0 98 175 0 0 155 76
TW.cpp 1.986 ns 1 clock 1 clock 0 0 98 175 0 0 155 76
MT_orig.cpp 7.226 ns 1258 clocks 1259 clocks 2 0 328 794 1 0 364 285
MT.cpp 6.508 ns 3 clocks 3 clocks 2 0 170 467 1 0 186 132
MT2.cpp 4.965 ns 1 clock 1 clock 2 0 162 435 1 0 198 164

References