FIFO source codes in RTL Verilog for any FPGA vendors

Please refer to: 泉知論, “同期FIFOのFPGAベンダ非依存記述と高速化設計”, 信学技報 VLD2014-147, CPSY2014-156, RECONF2014-80, 2015年1月.

documents

fifo4any.v: synthesizable FIFO source codes in RTL Verilog for any FPGA vendors
mempipe.v: synthesizable memory source codes in RTL Verilog for any FPGA vendors

mem0pipe_module, mem1pipe_module, mem2pipe_module in mempipe.v

module memory_module(clk, a, d, q, we); //: parameter DW; // bit-width of data; parameter AW; // bit-width of address; parameter SZ; // size of memory, i.e. SZ=2^AW; input clk; // clock signal; input [AW-1:0] a; // address; input we; // write enable, 0:read, 1:write; input [DW-1:0] d; // write data; output [DW-1:0] q; // read data

fiforeg_module, fifo2t_module, fifo_module in fifo4any.v

module fifo_module(xrst, clk, idata, ivalid, iwait, odata, ovalid, owait, count, clr); // in fifo4any.v: parameter DW; // bit-width of data; parameter AW; // bit-width of address; parameter SZ; // size of memory, i.e. SZ=2^AW; input xrst, clk; // asynchronous reset(negative), clock signal; input [DW-1:0] idata; // input data; input ivalid; // valid signal to control input transfer; output iwait; // wait signal to control input transfer; output [DW-1:0] odata; // output data; output ovalid; // valid signal to control output transfer; input owait; // wait signal to control output transfer; output [AW:0] count; // number of data in FIFO, [AW+1:0] for fifo_module; input clr; // clear FIFO

The capacity of FIFO is SZ for fiforeg_module, SZ+4 for fifo2t_module, and 2*(SZ+4) for fifo_module.
Data transfer is controlled by sender's valid and receiver's wait signals, where data is transfered at the cycle if and only if (valid==1)&&(wait==0). Read timing is equivalent to "first-word fall-through" mode for Xilinx or "show-ahead" mode for Altera

mem0pipe_module: Memory module without delay.; Synthesizers use no BRAMs but registers and logics to implement this. Applicable only for small size memory.
mem1pipe_module: Pipelined memory module with 1cycle delay.; Synthesizers may use BRAMs.
mem2pipe_module: Pipelined memory module with 2cycle delay.; Synthesizers may use BRAMs, safer than mem1pipe.
fiforeg_module: FIFO module with registers. Applicable only for small size FIFO; Fastest (throughput ... 1cycles per 1data, latency ... 1cycle).
fifo2t_module: FIFO module with single BRAM.; Relatively slow (throughput ... 2cycles per 1data, latency ... 4cycles).; fiforeg_module and mem2pipe_module are used.
fifo_module: FIFO module with double BRAMs.; Fast (throughput ... 1cycles per 1data, latency ... 6cycles).; fifo2t_module, fiforeg_module and mem2pipe_module are used.